The present invention relates to microelectronic devices, and more particularly to power semiconductor devices.
High voltage silicon carbide (SiC) devices can handle voltages above about 600V or more. Such devices may handle as much as about 100 amps or more of current, depending on their active area. High voltage SiC devices have a number of important applications, particularly in the field of power conditioning, distribution and control. High voltage semiconductor devices, such as Schottky diodes, MOSFETs, GTOs, IGBTs, BJTs, etc., have been fabricated using silicon carbide.
A conventional SiC power device, such as a SiC Schottky diode structure, has an n-type SiC substrate on which an n− epitaxial layer, which functions as a drift region, is formed. The device typically includes a Schottky contact formed directly on the n− layer. Surrounding the Schottky contact is a p-type JTE (junction termination extension) region that is typically formed by ion implantation. The implants may be aluminum, boron, or any other suitable p-type dopant. The purpose of the JTE region is to reduce electric field crowding at the edges of the junction, and to reduce or prevent the depletion region from interacting with the surface of the device. Surface effects may cause the depletion region to spread unevenly, which may adversely affect the breakdown voltage of the device. Other termination techniques include guard rings and floating field rings that may be more strongly influenced by surface effects. A channel stop region may also be formed by implantation of n-type dopants, such as nitrogen or phosphorus, in order to reduce extension of the depletion region toward the edge of the device.
In addition to junction termination extension (JTE), multiple floating guard rings (MFGR) and field plates (FP) are commonly used termination schemes in high voltage silicon carbide devices. Another conventional edge termination technique is a mesa edge termination. However, the presence of a mesa termination may cause a high electric field to occur at the mesa corner, even if a junction termination extension or guard ring is present. Over-etching of the mesa can exacerbate the problem of electric field crowding at the mesa corner. A high electric field at the mesa corner may result in a much lower breakdown voltage than would otherwise be expected for a given drift layer thickness and doping.
A conventional mesa-terminated PIN diode is illustrated in FIG. 1. As shown therein, a PIN diode 10 includes an n− drift layer 12 between a p+ layer 16 and an n+ substrate 14. FIG. 1 illustrates one half of a PIN-stricture; the structure may include mirror image portions (not shown). An anode contact 23 is on the p+ layer 16, and a cathode contact 25 is on the n+ substrate 14. The p+ layer 16 is formed as a mesa on the n− drift layer 12. A junction termination extension (JTE) region 20 including a plurality of JTE zones 20A, 20B, 20C is provided in the n− drift layer 12 adjacent the p+ mesa 16. The JTE zones 20A, 20B, 20C are p-type regions that may have levels of charge that decrease outwardly with distance from the PN junction between the p+ mesa 16 and the n− drift layer 12. Although three JTE zones 20A, 20B, 20C are illustrated, more or fewer JTE zones may be provided.
As shown in FIG. 1, the n− drift layer 12 adjacent the p+ mesa 16 may be slightly over-etched due, for example, to difficulties in etch process control, so that a sidewall 12A of the n− drift layer 12 beneath the p+ mesa 16 may be exposed. Over-etching of up to about 3000 Å may occur in some cases. To protect the exposed sidewall 12A, a sidewall implant may be performed in which p-type impurities are implanted into the sidewall 12A to form a sidewall implant region 22.
In conventional mesa-terminated structures, such as the PIN diode structure 10 illustrated in FIG. 1, field crowding may occur at or near the mesa corners 29, resulting in high electric field strengths at the corners 29. These high field strengths can reduce the breakdown voltage of the device. For example, a conventional mesa-terminated PIN diode structure that has a theoretical breakdown voltage of 12 kV, based on thickness and doping of the drift layer and the JTE design, may have an effective breakdown voltage of only 8 kV.
In addition to field crowding, another challenge in the development of SiC power bipolar junction transistors (BJTs) is the phenomenon of current gain degradation, that is, a reduction in current gain over time in the device. Current gain degradation is typically attributed to material defects such as basal plane dislocations (BPDs) and to surface recombination, especially along the emitter sidewall and to surface of the base of the device. A slight reduction of current gain degradation on SiC BJTs fabricated on BPD-free wafers has been observed. In addition, the emitter fingers of SiC BJTs are typically formed by reactive ion etching (RIE). The non-uniformity of RIE etching rate can partially or completely etch away the base material around the wafer periphery, which can cause a large reduction in yields.